By Nicolas Mokhoff
Integrated System Design
Posted 12/05/01, 03:42:51 PM EDT

New classes of systems-on-chip are presenting unique technical and economic challenges. Not only does the design activity engage the best intelligence of the design community, but it also poses verification hurdles for the test world.

As one panelist from IBM put it last month at the International Test Conference: The interdependency of design, EDA tools and test engineering will become stronger, and comprehensive technical and economic analysis of the design-for-test and test strategies, as part of the whole design process, will become paramount.

As we prepared next-year's editorial calendar, that interdependency of disciplines was our guiding idea in terms of choosing the appropriate topics to feature. ISD will continue to provide design process information and knowledge in a monthly journal written by your peers. We look forward to deepening this relationship next year as we embark on a new journey with SoC design at its center.

With the continuing march toward placing more transistors on each new SoC comes the added burden of necessary SoC test strategies. As such, verification and test subjects populate our 2002 editorial calendar, which can be found on our Web site (isdmag.com).

Besides verification, we will have monthly features in the categories of architectural design; implementation of systems in silicon; and overall design, the latter zeroing in on design-management and design-closure topics on alternate months.

Design teams will report on their methodologies for achieving design closure. Topics will include timing closure, signal integrity, power analysis and testability. Design managers will write on the contemporary challenges of IC design-team management, including recruiting key specialists, keeping computing resources ahead of demand and managing a geographically dispersed design team.

And, of course, each month ISD will spotlight a particular new chip design, with a description of the chip and a discussion of the high points of the design process, in the words of the engineers who did the work. With shrinking market windows, we expect many of our readers will be eager to feature their SoC design and methodology as the cover story.

In addition, our monthly "Working Papers" section will consist of short reports from design teams on how they are tackling the most pressing chip-design problems. Our staff-written look behind some recent announcements in the IC and EDA worlds, from the point of view of the chip-design team, can be found in "Behind the News."

So sit down, put your feet up and read this month's issue. Then take pen to paper-or mouse to pad-and start scribbling notes for what is sure to result in a gratifying publishing experience.

We invite members of IC design teams to contribute articles based on their firsthand experience, discussing problems and solutions the teams faced and resolved during actual chip-design work. Submit your ideas to editorial director Ron Wilson (rwilson@cmp.com), the plenipotentiary of ISD, and remember that the purpose is to share your experiences-positive and negative-with other designers.

http://www.isdmag.com
© 2001 CMP Media LLC.
12/1/01, Issue # 13150, page 6.